When oscilloscopes are used to monitor a repetitive waveform, a trigger signal can be derived from the input signal by generating a trigger signal whenever the amplitude of the input signal exceeds a user controlled or automatically determined threshold. Typically, the user is provided with a level control to establish the triggering threshold and a slope .+-.control to determine whether the positive-going transition or the negative-going transition is to initiate the trigger signal.
To obtain a stable waveform display, it is necessary to trigger at an identical trigger point on the series of repetitive waveforms. U.S. Pat. No. 4,647,862 to Blair for a "Trigger Holdoff System tier a Digital Oscilloscope", hereby incorporated by reference, discloses one means for triggering at an identical point on a series of repetitive waveforms. A holdoff signal is used to provide a time delay between desired trigger events so that undesired events cannot cause an acquisition. The holdoff signal can thus be used to synchronize complex repetitive waveforms so that they appear stationary on a digital storage oscilloscope display.
In a digital storage oscilloscope, it is impossible to know in advance the time that an external, asynchronous signal will arrive in relation to the synchronous, internal clock system of the instrument. Since the holdoff signal mentioned above can be either an asynchronous signal or a signal that is synchronous with the internal clock, and the incoming triggering event is necessarily asynchronous to it, the use of these signals in the same circuit means that eventually the two signals will have every possible random timing relationship with each other. When digital circuit elements are exposed to mutually asynchronous inputs, a condition known as "metastability" can result. Metastability describes unpredictable and unreliable behaviors of a digital signal that can occur in the presence of asynchronous signals. For example, the output of a flip-flop exposed to such inputs can wander between defined logic states for an unpredictable amount of time. For additional background on the phenomenon of metastability, see "General Theory of Metastable Operation" by Leonard R. Marino from the IEEE Transactions on Computers, Vol. C-30, No. 2, February 1981.
Metastable behaviors in the trigger circuitry can lead to jitter and other undesirable clutter in the display. U.S. Pat. No. 5,122,694 to Bradford et al. for a "Method and Electrical Circuit for Eliminating Time Jitter Caused By Metastable Conditions in Asynchronous Logic Circuits", hereby incorporated by reference, discloses a circuit for generating a warning signal when input signal timing conditions are such as might permit metastable behaviors to occur. The warning signal can then be used to prevent triggering based on trigger signals that might be subject to metastable behaviors.
As the role of digital storage oscilloscopes has expanded, applications have been found that take advantage of the abilty of these instruments to record and display at a later time waveforms that are not repetitive. These applications can require triggering capabilities that focus on rare or anomalous occurrences, as opposed to repetitive signals. When the operation of digital circuitry is being analyzed, departures from normal digital signal behavior may constitute the events that are of interest to the user. U.S. Pat. No. 5,097,147 to Stuebing et al. for a "Limited Amplitude Signal Trigger Circuit", hereby incorporated by reference, discloses a trigger generation circuit that compares an input signal to two different thresholds and only generates a trigger output when the amplitude of the input signal crosses one threshold twice without having crossed the other threshold in-between. This type of circuit is used to detect a faulty digital signal that leaves one defined logic state, but fails to reach the other defined logic state.
As digital oscilloscopes have become increasingly used to monitor the behavior of signals in a complex digital environment, they have been equipped with triggering capabilities that are more appropriate to an environment with numerous digital signals. One such capability is the ability to establish a desired trigger time based on a Boolean combination of logic states of a number of digital signals. U.S. Pat. No. 4,585,975 to Wimmer for a "High Speed Boolean Logic Trigger Oscilloscope Vertical Amplifier with Edge Sensitivity and Nested Trigger", hereby incorporated by reference, discloses an oscilloscope having triggering capabilities resembling those used in logic analyzers, instruments designed to monitor the activities of a large number of digital signal lines simultaneously. It can be programmed to trigger when a particular parallel "word" (pattern) appears on the signal lines that it is monitoring. It can also be programmed to wait until a word has persisted for a specified time, or to trigger on a sequence of words appearing in a specified order. It can also produce triggers in response to particular edge transitions while other signals are in a specified state.
Set up and hold times are specifications that define, respectively, the time before a clock signal that data should be present and stable to guarantee that it is properly accepted and the time after a clock signal that data should continue to be present and stable to provide the same guarantee. Since failure to provide stable data during these intervals can lead to metastable conditions and improper circuit operation, being able to identify such occurrences is a highly desirable feature of a logic analyzer or an oscilloscope.
U.S. Pat. No. 4,968,902 to Jackson for an "Unstable Data Recognition Circuit for Dual Threshold Synchronous Data", hereby incorporated by reference, discloses a circuit that allows digital data acquisition instruments to recognized when data is monitored with dual thresholds. The dual thresholds are typically set to correspond to the voltage levels that define a clear logic "1" and a clear logic "0", with gap between them defining an undeterminate logic level, or transitional state. During the time that a signal's voltage level is between levels an "unstable" signal is generated. Local unstable signals for a single line may be ORed together to produce an unstable signal for a collection of data signals. If the digital data lingers between the dual thresholds for too long, a problem is indicated. By measuring the time from the beginning of an unstable signal to the occurrence of the active clock edge, set up time violations can be detected. And, by measuring the time from the active clock edge to the end of the unstable signal, hold time violations can be measured.
The circuitry described in the '902 Jackson patent is suitable for use in a logic analyzer, where precise trigger placement is not extremely important, but its usefulness for oscilloscopes is limited by its lack of trigger placement precision. When this circuit monitors hold time violations, the resulting trigger is referenced to the end of the violation, rather than to the active clock edge at the beginning of the hold time that created the violation. In a logic analyzer this would be good enough, since the trigger would then be associated with the next acquisition clock pulse, but in an oscilloscope with a higher sample rate in which it is desired to precisely position the trigger location this imprecision is not satisfactory.
U.S. Pat. No. 5,124,597 to Stuebing et al. for a "Timer Circuit Including an Analog Ramp Generator and a CMOS Counter", hereby incorporated by reference, discloses a timer circuit and several applications for that timer circuit including triggering on a pulse width within limits, triggering on a pulse width that is outside of limits, and triggering on glitches of either polarity.
A more complex apparatus for generating a trigger signal is described in U.S. Pat. No. 4,823,076 to Haines et al. for a "Method and Apparatus for Triggering", hereby incorporated by reference. The apparatus disclosed in this patent includes a word recognizer and a state machine, the state machine including timing means. This circuitry can produce clock-based trigger modes and time-based trigger modes. The clock based trigger modes include single event triggering, nested event triggering, and consecutive and exception event triggering. The time-based trigger modes include all of the same modes as are available in the clock-based modes, plus set up and hold time triggering, transition time triggering, and sliver pulse triggering. This patent also includes a fairly comprehensive review of the prior art capabilities provided by the instruments produced by several manufacturers.
While the apparatus disclosed in the Haines et al. patent described above is capable of producing a trigger in response either set up time violations or hold time violations, it requires a lot of circuitry and it would be desirable to find a simpler approach. And, while the circuitry shown in Haines et al. has a mode in which it is capable of producing a trigger in response to a set up violation, and another mode in which it is capable of producing a trigger in response to a hold violation, it does not have a mode in which it produces such a trigger in response to either a set up time violation or a hold time violation in the same waveform acquisition.
Another limitation of the approach taken in the Haines et al. patent is the fact that the triggers that it produces in the set up time violation mode have their timing determined by and referenced to the timing of the user's clock signal, while the triggers that it produces in the hold time violation mode have their timing determined by and referenced to the timing of the user's data signal. It would be preferable if triggers caused by both types of violations were determined by and referenced to the user's clock signal.